1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing and more specifically to a bi-layer silicon film and its method of fabrication.
2. Discussion of Related Art
In order to fabricate more complex and higher density integrated circuits such as microprocessors and memories, the size of device features must be continually reduced. An important feature which must be reduced in order to increase device density is the polysilicon gate length and correspondingly the polysilicon thickness of MOS transistors. Present polysilicon deposition processes form polysilicon films 802 having large and columnar grains 804 as shown in FIG. 6. The large and columnar grains 804 are beginning to play a critical role in the performance of the transistor as transistor gate lengths are shrunk to less than 0.18 microns. Dopants 806 which are subsequently added to the polysilicon film in order to reduce the resistance of the film utilize the grain boundaries 808 to diffuse throughout the polysilicon film 802. During subsequent thermal anneal steps used to drive and activate the dopants diffusion is restricted to the long columnar grain boundaries 808 causing areas 810 of undoped polysilicon, which is especially a problem at the polysilicon 802/gate dielectric 812 interface. The lack of uniform distribution of dopants in the polysilicon, known as “poly depletion”, detrimentally affects the performance of the fabricated transistor especially as a gate lengths decrease to below 0.18 microns. Additionally, during dopant drive and activation anneals the long columnar grain boundaries 808 provide a path for fast diffusion of dopants 806 to the gate/dielectric interface where they can penetrate the dielectric and alter the electrical performance of the device.